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19-2419; rev 6; 10/14 max5048 7.6a, 12ns, sot23/tdfn, mosfet driver for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maximintegrated.com. general description the max5048a/max5048b are high-speed mosfetdrivers capable of sinking/sourcing 7.6a/1.3a peak cur- rents. these devices take logic input signals and drive a large external mosfet. the max5048a/max5048b have inverting and noninverting inputs that give the user greater flexibility in controlling the mosfet. they feature two separate outputs working in complementary mode, offering flexibility in controlling both turn-on and turn-off switching speeds. the max5048a/max5048b have internal logic circuitry, which prevents shoot-through during output state changes. the logic inputs are protected against volt- age spikes up to +14v, regardless of v+ voltage. propagation delay time is minimized and matched between the inverting and noninverting inputs. the max5048a/max5048b have very fast switching times combined with very short propagation delays (12ns typ), making them ideal for high-frequency circuits. the max5048a/max5048b operate from a +4v to +12.6v single power supply and typically consume 0.95ma of supply current. the max5048a has cmos input logic levels, while the max5048b has standard ttl input logic levels. these devices are available in space-saving 6-pin sot23 and tdfn packages. applications power mosfet switchingswitch-mode power supplies dc-dc converters motor control power-supply modules features ? independent source-and-sink outputs forcontrollable rise and fall times ? +4v to +12.6v single power supply ? 7.6a/1.3a peak sink/source drive current ? 0.23 open-drain n-channel sink output ? 2 open-drain p-channel source output ? 12ns (typ) propagation delay ? matching delay time between inverting andnoninverting inputs ? v cc /2 cmos (max5048a)/ttl (max5048b) logic inputs ? 1.6v input hysteresis ? up to +14v logic inputs (regardless of v+voltage) ? low input capacitance: 2.5pf (typ) ? -40? to +125? operating temperature range ? 6-pin sot23 and tdfn packages p_out gnd n_out 1 + 6 in+ 5 in- v+ max5048amax5048b sot23 top view 234 pin configurations typical operating circuit ordering information max5048amax5048b p_out n_out in- gnd in+ v+ v+ n part temp range pin- package logic input top mark max5048aaut-t -40? to +125? 6 sot23 v cc /2 cmos abec max5048baut-t -40? to +125? 6 sot23 ttl abed max5048aatt-t -40? to +125? 6 tdfn-ep* v cc /2 cmos akv max5048batt-t -40? to +125? 6 tdfn-ep* ttl akw pin configurations continued at end of data sheet. + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. * ep = exposed pad. downloaded from: http:///
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 2 maxim integrated absolute maximum ratings electrical characteristics(v+ = +12v, t a = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 3) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltages referenced to gnd v+ ...........................................................................-0.3v to +13v in+, in-...................................................................-0.3v to +14v n_out, p_out ............................................-0.3v to (v+ + 0.3v) n_out continuous output current (note 1) ....................390ma p_out continuous output current (note 1).....................100ma continuous power dissipation* (t a = +70?) 6-pin sot23 (derate 9.1mw/? above +70?)............727mw 6-pin tdfn (derate 18.2mw/? above +70?) .........1454mw operating temperature range .........................-40? to +125? storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? note 1: continuous output current is limited by the power dissipation of the package. *as per jedec51 standard. parameter symbol conditions min typ max units power supply v+ operating range v+ 4.0 12.6 v v+ undervoltage lockout uvlo v+ rising 3.25 3.6 4.00 v v+ undervoltage lockouthysteresis 400 mv v+ undervoltage lockout tooutput delay time v+ rising 300 ns v+ supply current i+ in+ = in- = v+ 0.95 1.5 ma n-channel output t a = +25? 0.23 0.32 v v+ = +10v, i n-out = -100ma t a = +125? 0.38 0.43 t a = +25? 0.24 0.34 driver output resistancepulling down (max5048aaut/ max5048baut) r on-n v v+ = +4.5v, i n-out = -100ma t a = +125? 0.40 0.47 t a = +25? 0.31 0.34 v v+ = +10v, i n-out = -100ma t a = +125? 0.46 0.51 t a = +25? 0.32 0.36 driver output resistancepulling down (max5048aatt/ max5048batt) r on-n v v+ = +4.5v, i n-out = -100ma t a = +125? 0.48 0.55 note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . package thermal characteristics (note 2) sot23 junction-to-case thermal resistance ( jc )......................75?/w tdfn junction-to-case thermal resistance ( jc ).......................8.5?/w downloaded from: http:///
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 3 maxim integrated electrical characteristics (continued)(v+ = +12v, t a = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 3) parameter symbol conditions min typ max units power-off pulldown resistance v+ = 0 or unconnected, i n-out = -10ma, t a = +25? 3.3 10 power-off pulldown clamp voltage v+ = 0 or unconnected, i n-out = -10ma, t a = +25? 0.85 1.0 v output leakage current i lk-n n_out = v+ 6.85 20 ? peak output current (sinking) i pk-n c l = 10,000pf 7.6 a p-channel output t a = +25? 2.00 3.00 v v+ = +10v, i p-out = 50ma t a = +125? 2.85 4.30 t a = +25? 2.20 3.30 driver output resistancepulling up (max5048aaut/ max5048baut) r on-p v v+ = +4.5v, i p-out = 50ma t a = +125? 3.10 4.70 t a = +25? 2.08 3.08 v v+ = +10v, i p-out = 50ma t a = +125? 2.93 4.38 t a = +25? 2.28 3.38 driver output resistancepulling up (max5048aatt/ max5048batt) r on-p v v+ = +4.5v, i p-out = 50ma t a = +125? 3.18 4.78 output leakage current i lk-p p_out = 0 0.001 10 ? peak output current (sourcing) i pk-p c l = 10,000pf 1.3 a logic input max5048a 0.67 x v+ logic 1 input voltage v ih max5048b 2.4 v max5048a 0.33 x v+ logic 0 input voltage v il max5048b 0.8 v max5048a 1.6 logic-input hysteresis v hys max5048b 0.68 v logic-input current v in_ = v+ or 0 0.001 10 ? input capacitance c in 2.5 pf switching characteristics for v+ = +10v c l = 1000pf 8 c l = 5000pf 45 rise time t r c l = 10,000pf 82 ns c l = 1000pf 3.2 c l = 5000pf 7.5 fall time t f c l = 10,000pf 12.5 ns turn-on propagation delay time t d-on figure 1, c l = 1000pf (note 4) 7 12 25 ns turn-off propagation delay time t d-off figure 1, c l = 1000pf (note 4) 7 12 25 ns break-before-make time 2.5 ns downloaded from: http:///
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 4 maxim integrated electrical characteristics (continued)(v+ = +12v, t a = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 2) note 3: all dc specifications are 100% tested at t a = +25?. specifications over -40? to +125? are guaranteed by design. note 4: guaranteed by design, not production tested. parameter symbol conditions min typ max units switching characteristics for v+ = +4.5v c l = 1000pf 12 c l = 5000pf 41 rise time t r c l = 10,000pf 74 ns c l = 1000pf 3.0 c l = 5000pf 7.0 fall time t f c l = 10,000pf 11.3 ns turn-on propagation delay time t d-on figure 1, c l = 1000pf (note 4) 8 14 27 ns turn-off propagation delay time t d-off figure 1, c l = 1000pf (note 4) 8 14 27 ns break-before-make time 4.2 ns typical operating characteristics (c l = 1000pf, t a = +25?, unless otherwise noted.) rise time vs. supply voltage max5048 toc01 supply voltage (v) rise time (ns) 10 8 6 8 11 14 17 20 5 41 2 t a = +125 c t a = 0 c t a = +85 c t a = +25 c t a = -40 c fall time vs. supply voltage max5048 toc02 supply voltage (v) fall time (ns) 10 8 6 2.5 3.5 4.5 5.0 6.02.0 41 2 t a = +125 c t a = -40 c t a = 0 c t a = +85 c t a = +25 c 3.0 5.54.0 max5048 toc03 supply voltage (v) propagation delay (ns) 10 8 6 12 14 16 18 2010 41 2 t a = +125 c t a = -40 c t a = 0 c t a = +85 c t a = +25 c propagation delay time, low-to-high vs. supply voltage downloaded from: http:///
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 5 maxim integrated typical operating characteristics (continued) (c l = 1000pf, t a = +25?, unless otherwise noted.) max5048 toc04 supply voltage (v) propagation delay (ns) 10 8 6 12 14 16 18 2010 41 2 t a = +125 c t a = -40 c t a = 0 c t a = +85 c t a = +25 c propagation delay time, high-to-low vs. supply voltage supply current vs. supply voltage max5048 toc05 supply voltage (v) supply current (ma) 10 8 6 2 4 6 8 10 12 0 41 2 duty cycle = 50%v+ = +10v, c l = 0 1mhz 500khz 40khz 75khz 100khz supply current vs. load capacitance max5048 toc06 load capacitance (pf) supply current (ma) 1600 1200 400 800 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0 2000 v+ = +10vf = 100khz duty cycle = 50% supply current vs. temperature max5048 toc07 temperature ( c) supply current (ma) 100 75 50 25 0 -25 1.3 1.4 1.5 1.6 1.7 1.81.2 -50 125 v+ = +10vf = 100khz, c l = 0 duty cycle = 50% max5048a input threshold voltage vs. supply voltage max5048 toc08 supply voltage (v) input threshold voltage (v) 10 8 6 1 2 3 4 5 6 7 80 41 2 rising falling max5048a supply current vs. input voltage max5048 toc09 input voltage (v) supply current (ma) 10 8 6 4 2 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.80.8 01 2 inputhigh-to-low inputlow-to-high downloaded from: http:///
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 6 maxim integrated input voltage vs. output voltage (v+ = +4v, c l = 5000pf) max5048 toc10 in+2v/div output2v/div 20ns/div input voltage vs. output voltage (v+ = +4v, c l = 10,000pf) max5048 toc11 in+2v/div output2v/div 20ns/div input voltage vs. output voltage (v+ = +4v, c l = 5000pf) max5048 toc12 in+2v/div output2v/div 20ns/div input voltage vs. output voltage (v+ = +4v, c l = 10,000pf) max5048 toc13 in+2v/div output2v/div 20ns/div input voltage vs. output voltage (v+ = +12v, c l = 5000pf) max5048 toc14 in+5v/div output5v/div 20ns/div input voltage vs. output voltage (v+ = +12v, c l = 10,000pf) max5048 toc15 in+5v/div output5v/div 20ns/div input voltage vs. output voltage (v+ = +12v, c l = 5000pf) max5048 toc16 in+5v/div output5v/div 20ns/div input voltage vs. output voltage (v+ = +12v, c l = 10,000pf) max5048 toc17 in+5v/div output5v/div 20ns/div typical operating characteristics (continued) (c l = 1000pf, t a = +25?, unless otherwise noted.) downloaded from: http:///
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 7 maxim integrated detailed description logic inputs the max5048a/max5048bs?logic inputs are protectedagainst voltage spikes up to +14v, regardless of the v+ voltage. the low 2.5pf input capacitance of the inputs reduces loading and increases switching speed. these devices have two inputs that give the user greater flexi- bility in controlling the mosfet. table 1 shows all pos- sible input combinations. the difference between the max5048a and the max5048b is the input threshold voltage. the max5048a has v cc /2 cmos logic-level thresholds, while the max5048b has ttl logic-level thresholds (seethe electrical characteristics ). for v+ above 5.5v, v ih (typ) = 0.5x(v+) + 0.8v and v il (typ) = 0.5x(v+) - 0.8v. as v+ is reduced from 5.5v to 4v, v ih and v il gradually approach v ih (typ) = 0.5x(v+) + 0.65v and v il (typ) = 0.5x(v+) - 0.65v. connect in+ to v+ or in- to gndwhen not used. alternatively, the unused input can be used as an on/off pin (see table 1). undervoltage lockout (uvlo) when v+ is below the uvlo threshold, the n-channelis on and the p-channel is off, independent of the state of the inputs. the uvlo is typically 3.6v with 400mv typical hysteresis to avoid chattering. driver outputs the max5048a/max5048b provide two separate out-puts. one is an open-drain p-channel, the other an open-drain n-channel. they have distinct current sourc- ing/sinking capabilities to independently control the rise and fall times of the mosfet gate. add a resistor in series with p_out/n_out to slow the corresponding rise/fall time of the mosfet gate. applications information supply bypassing, device grounding, and placement ample supply bypassing and device grounding areextremely important because when large external capacitive loads are driven, the peak current at the v+ pin can approach 1.3a, while at the gnd pin the peak current can approach 7.6a. v cc drops and ground shifts are forms of negative feedback for inverters and, ifexcessive, can cause multiple switching when the in- input is used and the input slew rate is low. the device driving the input should be referenced to the max5048a/max5048b gnd pin especially when the in- input is used. ground shifts due to insufficient device grounding may disturb other circuits sharing the same ac ground return path. any series inductance in the v+, p_out, n_out and/or gnd paths can cause oscilla- tions due to the very high di/dt that results when the max5048a/max5048b are switched with any capacitive load. a 0.1? or larger value ceramic capacitor is rec- ommended bypassing v+ to gnd and placed as close to the pins as possible. when driving very large loads (e.g., 10nf) at minimum rise time, 10? or more of paral- lel storage capacitance is recommended. a ground plane is highly recommended to minimize ground return resistance and series inductance. care should be taken to place the max5048a/max5048b as close as possi- ble to the external mosfet being driven to further mini- mize board inductance and ac path resistance. power dissipation power dissipation of the max5048a/max5048b con-sists of three components, caused by the quiescent current, capacitive charge and discharge of internal nodes, and the output current (either capacitive or resistive load). the sum of these components must be kept below the maximum power-dissipation limit. pin description pin name function 1v + power supply. bypass to gnd with a0.1? ceramic capacitor. 2 p_out p-channel open-drain output. sourcescurrent for mosfet turn-on. 3 n_out n-channel open-drain output. sinkscurrent for mosfet turn-off. 4 gnd ground 5i n - inverting logic input terminal. connectto gnd when not used. 6 in+ noninverting logic input terminal.connect to v+ when not used. ? p exposed paddle. connect to gnd.solder ep to the gnd plane for improved thermal performance. in+ in- p-channel n-channel l l off on l h off on h l on off h h off on table 1. truth table l = logic low h = logic high downloaded from: http:///
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 8 maxim integrated the quiescent current is 0.95ma typical. the currentrequired to charge and discharge the internal nodes is frequency dependent (see the typical operating characteristics ). the max5048a/max5048b power dis- sipation when driving a ground referenced resistiveload is: p = d x r on(max) x i load 2 where d is the fraction of the period the max5048a/max5048bs?output pulls high, r on (max) is the maxi- mum on-resistance of the device with the output high(p-channel), and i load is the output load current of the max5048a/max5048b.for capacitive loads, the power dissipation is: p = c load x (v+) 2 x freq where c load is the capacitive load, v+ is the supply voltage, and freq is the switching frequency. layout information the mosfet drivers max5048a/max5048b source-and-sink large currents to create very fast rise and fall edges at the gate of the switching mosfet. the high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. the following pcb layout guidelines are recommended when designing with the max5048a/max5048b: place one or more 0.1? decoupling ceramic capaci- tor(s) from v+ to gnd as close to the device as possi-ble. at least one storage capacitor of 10? (min) should be located on the pc board with a low resis- tance path to the v+ pin of the max5048a/max5048b. there are two ac current loops formed between the device and the gate of the mosfet being driven.the mosfet looks like a large capacitance from gate to source when the gate is being pulled low. the active current loop is from n_out of the max5048a/max5048b to the mosfet gate to the mosfet source and to gnd of the max5048a/ max5048b. when the gate of the mosfet is being pulled high, the active current loop is from p_out of the max5048a/max5048b to the mosfet gate to the mosfet source to the gnd terminal of the decoupling capacitor to the v+ terminal of the decoupling capacitor and to the v+ terminal of the max5048a/max5048b. while the charging current loop is important, the discharging current loop is crit- ical. it is important to minimize the physical distance and the impedance in these ac current paths. in a multilayer pcb, the component surface layer surrounding the max5048a/max5048b should con-sist of a gnd plane containing the discharging and charging current loops. in+ v il 90%10% t d?off p_out and n_out tied together t d?on t f t r in+in- v+ v+ c l n_out gnd p_out test circuit timing diagram max5048amax5048b input output v ih figure 1. timing diagram and test circuit downloaded from: http:///
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 9 maxim integrated break- before- make control p n n_outgnd in- in+ p_out v+ max5048amax5048b figure 2. max5048a/max5048b functional diagram max5048a max5048b p_out n_out in- gnd in+ v+ v s v+ (4v to 12.6v) figure 3. noninverting application max5048a max5048b p_out n_out in- gnd in+ v+ v s v out from pwm controller (boost) v+ (4v to 12.6v) figure 4. boost converter max5048a max5048b p_out n_out in- gnd in+ v+ max5048a/ max5048b p_out n_out in- gnd in+ v+ from pwm controller (buck) v out 4v to 12v p n figure 5. max5048a/max5048b in high-power synchronous buck converter downloaded from: http:///
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 10 maxim integrated p_out gnd n_out 1 + 6 in+ 5 in- v+ max5048amax5048b tdfn-ep (3mm x 3mm) top view 23 exposed pad 4 pin configurations (continued) package information for the latest package outline information and land patterns (foot-prints), go to www.maximintegrated.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only.package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 6 sot23 u6f+6 21-0058 90-0175 6 tdfn 21-0137 90-0058 chip information process: bicmos downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ________________________________ 11 2014 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max5048 7.6a, 12ns, sot23/tdfn, mosfet driver revision history revision number revision date description pages changed 5 11/12 added ??lead(pb)-free/rohs-compliant designations to ordering information 1, 9 6 10/14 updated driver output resistance?ulling down specifications 2 downloaded from: http:///

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